Topic: Multiple threshold voltage placement optimization

nContinous trend in scaling of CMOS reduce the feature size and increase the integration of Transistor on chip.
nThese forces the sub threshold Leakage current overrides the dynamic power.
nTo reduce the Leakage current , the Technique of multiple threshold voltage placement optimization is applied.

nThe objective is to reduce leakage current by applying multiple threshold voltage technique which can be used as an optimization tool.
nIn the basic VLSI Design flow this work comes after placement and before routing.

nIn these multi Vt Optimization method, low Vt, High Vt cells are taken
nLow Vt are faster Transistor but have high leakage power and are used for timing critical path.
nHigh Vt cells are slower Transistor but have low leakage power compared to low Vt cells and are used for non-timing critical path.

nThe gate level netlist with single threshold voltage cells are taken
nAfter doing the floorplan and placement, the critic
nConsider the design is work at 90nm Technology
nThe critical path is found to be 2,4,5,6,8 and it is operating at 360 MHz
nLeakage power found to be 21.6mw
nThe non critical path replace with High Vth cells which are slower Transistor and it is operated in 200MHZ.
nLeakage power after assign High Vth is 9.7mwal path for the circuit with single threshold voltage cell are found and analyzed .
nThe design is checked for timing, if the slack is zero or positive
nThen swap the cells in the non critical path with high threshold voltage and in the critical path with low threshold voltage cells by maintaining the timing,

nLeakage current is reduced to the optimal value.
nSystem performance is maintained constant.